With the demand for higher levels of integrated circuits of semiconductor chips, such as silicon semiconductor chips, and the need for greater density in these circuits, the spacing between the gates of field effect transistors (FET) in forming local interconnects to the source and drain of the FET, becomes more and more critical. This is specially the case with a microprocessor integrated circuit chip of which a large portion of the real estate of the chip is an SRAM. For increased performance of future microprocessor, the storage capacity of the SRAM must increase thereby requiring a larger portion of real estate of the microprocessor.
Since the field effective transistor (FET) is fabricated prior to the formation of the local interconnects, the lithographic mask design provides for additional space between local interconnect openings and the polysilicon gate to prevent accidental shorting the source and/or drain to the gate. This margin of error in the layout design wastes valuable real estate of the silicon wafer. Therefore, it would be desirable to create minimum spaced local interconnects without regard to the presence of the gate of the FET in the spaces between the local interconnects.